The present invention relates to a DMA (Direct Memory Access) controller and, particularly, to a DMA controller which executes a DMA data transfer according to a 2-bus cycle transfer manner.
As well known in the art, a DMA controller is used for executing a data transfer between a peripheral input/output device (referred to as "peripheral I/O", hereinafter) such as a magnetic disc device, a communication device, or display device and a main storage device (referred to as "memory", hereinafter) in lieu of a central processing unit (CPU).
With improvement of processing efficiency and speed of CPU, a data bus width thereof is increased to 32 bits, for example. When an information processing system is constructed by using a CPU having such a large data bus width, not all of the peripheral I/Os to be used in the same system may have the same bus width as that of the CPU. For example, peripheral I/Os having 8-bit (1-byte) and/or 16-bit (half word) bus width may be used for a CPU having 32-bit (1 word) bus width. In such case, a DMA data transfer is required between a memory and peripheral I/Os having bus widths different from each other.
To this end, a DMA controller of a 2-bus cycle transfer type is used. The 2-bus cycle transfer system is such that the data transfer is performed by a read bus cycle and a write bus cycle. Such DMA controller executes the read cycle first to fetch data from a data source unit such as a memory or a peripheral I/O, then internally rearranges or aligns fetched data in accordance with a bus width and/or a storing address of a data destination unit such as a peripheral I/O or a memory, and thereafter executes the write bus cycle to write the rearranged data in the data destination unit.
Thus, the DMA controller of the 2-bus cycle transfer type is required to rearrange or align the data fetched from the data source unit in order to perform a DMA transfer between ,the peripheral I/O and the memory having different bus widths. This rearrangement or alignment procedure can be completed within a read cycle if the operating frequency is low. However, when, in order to improve the transfer speed, the bus cycle is shortened by increasing operating frequency, it becomes impossible to complete such a rearrangement or alignment within the read bus cycle and, therefore, it is necessary to provide a time interval between the two bus cycles for such rearrangement. That is, it is impossible to execute the read bus cycle and the write bus cycle continuously, so that the improvement in transfer speed is restricted.